The present invention relates generally to digital signal processing hardware, and more specifically, to a processor for obtaining the Discrete Fourier Transform (DFT) of a digital signal.
The Discrete Fourier Transform (DFT) of a digital signal represents the spectral content of the signal. Processors for obtaining the DFT of a signal are commonly used for spectral analysis and filtering of digital signals.
Considerable design effort during the last 20 years has been directed at simplifying the arithmetic hardware in DFT processors in order to improve processing speed and reduce costs. Many such designs implement a large-radix DFT by cascading two or more stages of smaller-radix DFT's.
These designs generally require large data storage memories between each DFT stage, and the memories often cost much more than the arithmetic elements, so that the DFT processor is undesireably costly.
Also, most DFT processor designs require tandem or double-buffered memories which take turns reading and writing because the data must be written into memory in one order and read out in a different order.